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VLSI Forum

UTS has formed a group of academicians who are very much interested in understanding and learning the VLSI design related concepts and tools. Under this forum very frequently we organize special lectures by senior engineers of UTS, invited talk by senior professors from various universities, hands on lab sessions on FPGA boards and group discussions.

There is no membership fees for this forum any faculty member can join the forum.

The VLSI forum has been launched by UTS VLSI design group, to provide a platform for rugular discussions for University faculty members and engieers from industry. However the initial focus will be given to provide technical expertise and hands on sessions on latest FPGA and VLSI tools.

VLSI forum student chapter conducting Seminar and design contest on RTL design using VHDL

Schedule

27 SEP 2009 (sunday)
10.00 - 12.00 Seminar on RTL coding using VHDL (industry oppertunities)
12.00 - 13.00 Design contest (related to digital design)
The winners of the contest will be awarded with cas prize and certificates.
Eligibility criteria: ECE or EIE final year students
Registration fees: FREE
For registration please contact: 040-23732798, 09440318188 or mail to info@unistring.com
Click here to download the brochure

General Schedule for the Forum Activities is as below.
Day	Every saturday (participants will get confirmation message on mails )
Lecture Session	09.30 - 11.00 hrs
Tea/coffee break	11.00 - 11.15 hrs
Lab Session	11.15 - 13.00 hrs
Venue	UTS, Ameerpet branch, Hyderabad.

Slides and other Technical Material
Introduction talk	Scope of VLSI forum, Prerequist etc
Lecture 1	VLSI design styles– An Introduction
Lecture 2	VHDL based design flow
Lecture 3	Combinational circuit design using VHDL
Lecture 4	VHDL coding for sequential logic design
Lecture 5	Programmble logic devices, Xilinx ISE design flow
	ISE project for 8 bit counter with chipscope files
Lecture 6	Timing issues in RTL design, Xilinx ISE timing analysis
Lecture 7	CMOS cell design issues Inverter layout and schematic files, Electric vlsi design system project file MOSIS design rules

Up coming Events:

Lecture 8 - VHDL Modeling and FPGA board verification of selected 74 series chip's logic.
Lecture 9 - Low power VLSI design issues

To register in UTS VLSI forum please mail to info@unistring.com info@unistring.com

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