This section of FAQs consists of several basic questions realted to Front end design issues related to Semicustom VLSI design.
What are HDLs?
HDL stands for Hardware Description Language. To day the most popular HDLs are VHDL and Verilog. Generally HDLs are used to describe the digital hardware.
What is VHDL?
VHDL stands for “Very High speed Integrated circuit Hardware Description Language”. This is used to describe digital hardware which can be used for computer based simulation and also for Synthesizing a digital circuit either for ASIC of FPGA.
What is Verilog?
Verilog is another Hardware Description language which is used in industry for simulating and synthesizing digital hardware.
What are essential things to be taken care while writing the VHDL code?
When we are writing VHDL code aiming for synthesis that is important to understand the relationship between the code constructs and actual hardware. That is every VHDL statements should infer some practical hardware. So that kind of VHDL code is synthesizable. But when our requirement is only simulation all the constructs of VHDL can be used.
What are different modeling styles used in writing VHDL code?
There are mainly three modeling styles used in VHDL to describe a digital circuit
Dataflow style of modeling,
Structural modeling
Behavioral modeling.
In dataflow style of modeling the logic is realized in the form of Boolean expression. In structural style of modeling the required logic is implemented as inter connection between smaller components, where as in behavioral modeling the required logic is implemented in sequential code which is also called behavioral code.
Is the behavioral code can be synthesized?
Yes, If the behavioral code is written properly then it is synthesizable, but all constructs of behavioral code are not synthesizable. So even a behavioral code can be synthesizable if it follows some rules.
The code which is used for a FPGA synthesis can we used for ASIC synthesis?
Broadly speaking answer is Yes. If the code is written by using general constructs of VHDL then it is useful for even ASIC synthesis, but where as the code written by assuming some special FPGA libraries than it is not synthesizable for ASIC.
Can VHDL and Verilog work together?
It is possible while realizing system one module may be implemented in VHDL and the other module we can be implemented in verilog and they can work together.
What is Mixed Signal in VLSI design?
Mixed signal VLSI design got different meaning in different contexts for broadly speaking in VLSI design when both analog and digital circuit concepts together are used to implement a circuit then it is called mixed signal in VLSI design. For Example that can be an analog to digital converter. In which one side we have analog issues where as the other side we have digital issues.
Is VHDL used for analog design?
The original VHDL is not suitable for analog design but today there are extensions for VHDL which are useful for describing an analog design. But these are only used for simulation up to some level.
Ex: AHDL (Analog Hardware Description Language)
AMS VHDL (Analog Mixed Signal and VHDL)
Is VHDL is Comparable to Verilog?
Since both VHDL and Verilog are Hardware Description languages. There are several constructs in VHDL, which have counter parts in Verilog Ex. The “process” in VHDL is comparable to “always” statements in verilog and the “signal” in VHDL is comparable to “wire” in verilog. There exists lot many similarities between VHDL and Verilog. Since both are designed for Hardware description.
Is VHDL is Object oriented or structure Language
VHDL is object oriented it has the concept of object and several other features which generally we see in object oriented programming languages. So VHDL has to be considered under category of object oriented. The VHDL is derived from programming language ADA which is object oriented language. A lot of concepts in object oriented are even applicable to VHDL.
Ex: Operator overloading, the concept of classes and Object etc.,
VHDL is not fully object oriented because certain important concepts of object oriented programming languages like inheritance is not supported in VHDL. So even VHDL object oriented but it is not fully object oriented languages.
Is Verilog is comparable to C?
Yes. Verilog language has lot of similarities with C. The operators, the expressions and several other constructs in verilog are comparable to C.
Which are the most widely used Hardware Description Languages today?
Today industry relies on two hardware description languages they are VHDL, Verilog
Why engineers prefer verilog today?
The main reason for giving high performance to Verilog is, It’s similarity to C programming language. Since most of the engineers are already familiar with c programming language it became easy for them to learn verilog. Today several EDA companies are offering full support to verilog this is also another important reason for prefer verilog in industry.
Please read the following article for comparing VHDL, Verilog and C programming languages.
VHDL is useful and both simulation and synthesis. The initial aim while designing the VHDL was only simulation. But later the language is extended and synthesis feature is added. So VHDL code can be used for synthesis of a digital circuit either an ASIC or FPGA.
What is an effort required to convert one VHDL code to make it suitable for synthesis?
If the hardware description language code is written in RTL form (Registers Transfer Level) then it is highly suitable for synthesis. Where as if the hardware description language code in behavioral form, which is a lengthy sequence code written to describe the system. Then it may not be suitable for synthesis or lot of effort is required in generating the hardware for that code.
What is RTL?
Register Transfer Level (RTL) is a technique in which the logic is described as a dataflow between various registers with appropriate combinational logic in between. RTL is a preferred coding style for synthesis in industry
Does anybody use HDL only for Simulation purpose?
Yes. Engineers may use hardware description language only for simulations purpose. In that case they are not worried about the synthesis of the code. Their aim is only to describe the functionality of the logic in hardware description language.
Can we use C for FPGA based design?
Yes. Today we have some compliers and Synthesizers which can understand c code and can generate a bit file which can be programmed on to FPGA. But not all the constructs of C are synthesizable. That means only a portion of C language can be used for hardware design.
What is Simulation?
Simulation (in the context of VLSI) is the process in which a circuit is the verified by subjecting it with appropriate test input. Typically simulation involves making a model (which can be either a VHDL code or Verilog code) and verifying it with appropriate test inputs.
What is Synthesis?
Synthesis is a process in which the model at higher abstraction level is converted to an implementable form. There are two types of synthesis technologies which are very popular in digital design. If we are generating a layout using cell libraries it is called ASIC synthesis, where as if we are generating a bit file to program an FPGA then it is called FPGA Synthesis.