Direct Digital Frequency synthesizers (LUT based): :
Category
Mobile Comm & Software Radio related cores
Language
VHDL /Verilog
Simulation
Yes – with any HDL simulator
Synthesis
Yes – For FPGA/ASIC
Target Applications
Programmable oscillators in generating
frequency hopping signals
In Digital down converters
Waveform generation applications in Instrumentation
FPGA based Automated test pattern generators
Very high speed frequency switching
Other Features
C programs to generate required LUTs (in VHDL/Verilog syntax) according to the bit length chosen.
Configurable for any bit precision
Fully modular architecture, can be easily modified for any application.
Capability to generate digital modulation signals (optional feature) such as ASK,FSK,PSK and QPSK etc.
Highly optimized units for FPGA based applications.
Brief Description:
In this DDFS core pure digital techniques are used to produce desired output waveforms with full digital control (also called Numerically Controlled Oscillator). The following figure shows the basic principle involved in generating waveforms with DDFS principle.
In the developed core the phase value is generated using the modulo 2 j overflowing property of a j-bit phase accumulator. The rate of the overflows is the output frequency.
Where ∆P is the phase increment word, j is the number of phase accumulator bits, f clk is the clock frequency and f out is the output frequency. The constraint for maximum value of fout in the above equation comes from the sampling theorem.
The phase increment word in above equation is an integer, therefore the frequency resolution is found by setting ∆P = 1.
This correspond to the smallest frequency change that the DDFS can produce. This also corresponds to the lowest frequency that can be produced by the DDFS for a given value of f clk and j (number of bits).
For detailed block diagram, with modulation and pattern generation capabilities refer the data sheet. The data sheet also gives the range of frequencies achievable on various Xilinx and Altera FPGAs.
DDFS based modulation for signal generation.
Configurable for any bit precision
Highly optimized solution for FPGA based SDR applications.
Capability to generate different types of noise signals.
Board solution can also be offered.
Brief Description:
The core is developed aiming at different requirements of digital communicate.
