Real time FFT calculation in signal processing applications
STFT based spectrum analysis in speech processing
As Digital filter bank in channelizers
Other Features
Available for 8/16/256/1024 point FFT, with real & complex inputs.
Decimation in Time / Decimation in frequency architecture
16-bit fixed point arithmetic
Overflow indicators at every butterfly stage
Fully scalable VHDL cores
Verified on Xilinx FPGAs
FPGA efficient arithmetic blocks are used for high performance
Hardware solution with chosen FPGA family can also be provided
The FFT is a faster version of the Discrete Fourier Transform (DFT). The FFT utilizes some clever algorithms to do the same thing as the DFT, but in much less time. The DFT is extremely important in the area of frequency (spectrum) analysis because it takes a discrete signal in the time domain and transforms that signal into its discrete frequency domain representation.
It is the speed and discrete nature of the FFT that allows us to analyze a rapidly changing signal's spectral characteristics with computer.
For synthesis results and performance comparison refer the data sheet of specific FFT core.
Complex computing applications
DSP on FPGA
Digital communications
Other Features
Available with 12/16/32 bit precision
Based on Fixed point arithmetic
Fully scalable architecture
Overflow indicators at every butterfly stage
Fully scalable VHDL cores
Occupies very less FPGA area
Hyperbolic function calculation (optional feature)
Brief Description:
CORDIC stands for “COordinate Rotation DIgital Computer”. This core can calculate the trigonometric functions of sine, cosine, magnitude and phase (arctangent) to a chosen precision ( 12/16/32 bit) using fixed point representation. It can also calculate hyperbolic functions . The core is designed according to wide range of DSP and Digital communication applications.
Fixed co-efficient FIR filtering
DSP on FPGA
Symbol shaping filters in digital communications
Other Features
C programs to generate required LUTs according to the filter coefficients
Available with 16/32 bit precision representation
Based on Fixed point arithmetic
Fully scalable architecture, can be easily modified for any filter length
Brief Description:
This core can realize a completely different FIR architecture based on the distributed arithmetic (DA) concept, which is an efficient technique for FPGA based MAC operation. In contrast to conventional sum-of-products architecture, in distributed arithmetic we always compute the sum of products of a specific bit b over all coefficients in one step. This is computed using a table and an accumulator with shifter. The structure of Distributed Arithmetic FIR filter is shown in the below figure.
Figure 1: DA based FIR filter structure
A 'C' program which, can generate the LUT contents according to the chosen filter coefficients will also be supplied along with the VHDL code of the filter. This C program along with the generic VHDL code can realize FIR filter on FPGA with in few minutes. The structure is fully synthesizable and verified on different FPGAs.
