Different FPGA efficient DPWM generation architectures
Input is 8-bit Duty cycle word
Tested on Xilinx FPGAs
Brief Description:
The three different DPWM generation architectures can meet different types of applications such as switching voltage regulator, DC motor control etc. The following table gives the performance comparison for the three architectures for Spartan 3E FPGA.
Parameter
Down Counter DPWM
Decoder based DPWM
Delayloop and Mux based DPWM
Number of Slices
29
473
206
Number of Slice Flip Flops
19
269
267
Number of 4 input LUTs
51
824
143
Number of bonded IOBs
11
11
7
Number of master CLKs
1
1
1
Maximum master clk required
185.874MHz
233.973MHz
145.096MHz
Maximum possible switching Frequency
726 KHz
914 KHz
566 KHz
For more technical details refer the product data sheet.
For pricing and more information contact us at : info@unistring.com
FPGA efficient Arithmetic Blocks
Category
FPGA based arithmetic circuits
Language
VHDL
Simulation
Yes – with any HDL simulator
Synthesis
Yes – For FPGA/ASIC
Target Applications
DSP on FPGA
FPGA based encryption and decryption algorithm.
Other Features
All blocks are tested and verified
Floating point arithmetic blocks are complied with IEEE 754 standard
Overflow detection and rounding off in all arithmetic blocks
Pipelined adders and multipliers, for high throughput
Distributed arithmetic, bit serial arithmetic principles are used more performance
Brief Description:
The following arithmetic blocks with synthesis models are available
Pipelined Adder for 2 ’ s complement addition
Pipelined Multiplier for 2 ’ s complement multiplication
Generic (configurable to any bit size) Fixed point adder
Generic Fixed point multiplier
Distributed arithmetic based MAC unit
Single precision Floating point Adder (IEEE 754 standard)
Single Precision Floating point multiplier (IEEE 754 standard)
For more technical details refer the product data sheet.
For pricing and more information contact us at : support@unistring.com