UTS in collaboration with IETE, Warangal sub centre has jointly conducted a seminar on “Basics of VLSI cell design" along with a demo using layout editor and SPICE tools “. This seminar was aimed to give an overall idea about using the lay out editors and SPICE tools in digital design. This seminar was conducted to bring the awareness in the students in usage of LT SPICE tool. The final year B Tech students from KITS Warangal, Jayamukhi engg College, KITS Huzurabad, Ramappa engg college, along with lecturers from eminent colleges in Warangal were among the few participated in the seminar. This seminar was organized at IETE conference Hall, Mayuri Hall, Hanamkonda, on 15th Sep 2007.
Seminar was started with an inaugural talk by Mr Krishna Reddy , secretary, IETE sub center, Warangal. He highlighted the recent achievements by Warangal sub center. He said that this event is just beginning to many more future activities conducted be IETE Warangal Sub center. After this inaugural talk Mr K Vasu from UTS has taken over